--- title: "Do Chip Fabs Need Clean Rooms? Why Fab Costs Keep Doubling" url: "https://goremy.ai/blog/articles/do-chip-fabs-need-clean-rooms-fab-cost-economics" author: Luis Chavez-Mattos editor: Luis Chavez-Mattos editor_title: Director, Product published: "2026-10-27T14:00:08.961Z" updated: "2026-10-27T14:00:12.157Z" topic: AI Industry & Strategy description: "An Intel executive asks whether chip fabs still need today's clean rooms as fab costs double every four to five years and a high-end EUV scanner nears $400M." --- # Do Chip Fabs Need Clean Rooms? Why Fab Costs Keep Doubling > An Intel executive asks whether chip fabs still need today's clean rooms as fab costs double every four to five years and a high-end EUV scanner nears $400M. Edited by Luis Chavez-Mattos, Director, Product ยท Published 2026-10-27 ## Do chip fabs really need clean rooms? Nobody has shown that they don't. An Intel executive recently called it a valid question, though, given fab economics. Building a fab has roughly doubled in cost every four to five years over the past few decades, and a high-end EUV scanner with its associated equipment runs about $400 million. The argument is that decades of risk-averse habit may have locked in processes, including clean room infrastructure, that nobody has re-examined from a clean slate. It is a thought exercise, not a roadmap. ## TL;DR - The cost to build a fab has been **doubling roughly every four to five years** across the last 20 to 40 years, according to an Intel executive. - **Lithography is the most expensive module**, and its cost is growing faster than the fab as a whole. - A high-end **EUV scanner and its associated equipment cost about $400 million** today. - Extrapolating that curve forward produces numbers that **don't make sense**, which is the motivation for rethinking the basics. - The executive floated questioning **clean rooms and inherited process flows**, but said no incumbent would willingly run that experiment. - Tools are not the only constraint. Fabs also need **power, water, consumables, and raw clean room space**. ## Why do fab costs keep doubling? The Intel executive described chip manufacturing as extremely capital heavy. Plot the cost of building a fab over 20, 30, or 40 years and the line roughly doubles every four to five years. No single cause was given in the discussion, but the pieces he pointed to are equipment, facilities, and the inputs a fab consumes. Lithography is the sharpest example. It is the most expensive module in the fab, and the cost of patterning has been rising at more than the overall doubling rate. Today a high-end EUV scanner plus its associated equipment costs around $400 million. He made the extrapolation explicit. If the trend simply continued, patterning cost four years later would be double that figure. He joked a number in the hundreds of billions, then corrected himself to $800 million, and said either way it doesn't make sense to keep drawing the line. Something has to change in how chips get made, or the economics stop working. ## What would a clean-slate approach to chipmaking look like? The executive framed it as a thought exercise: are there radically different things we could do today that we couldn't do 20 years ago? He said the answer is probably "all of the above," which covers several layers: - **Transistor architecture.** The silicon transistor has kept evolving for 30 to 40 years, from planar to FinFETs to gate-all-around. That roadmap is well defined and many people are working on it. - **Process flow.** Fewer lithography passes would cut spending on the most expensive module. The interviewer raised this idea, and the executive did not rule it out. - **Infrastructure.** Do you need a clean room, and facilities as sophisticated and complex as today's? - **Chip design.** He noted that many CPU design methods were probably locked in about 30 years ago and may not still be the smartest way to work. He did not claim to have answers on any of these. He argued only that the economics make the questions worth asking. ## Could a fab run without a clean room? Not today, and not on anyone's production line. The interviewer joked about letting people eat hamburgers and smoke cigars in a research lab to see what happens to yield. The executive agreed it would be a great experiment, but said no incumbent such as Intel, TSMC, or Samsung would willingly do it. The reason is risk. Companies put tens of billions of dollars into a fab, and every day of lost productivity costs a great deal. The interviewer pointed out that you would save enormous sums by not building clean rooms. The executive's reply was that the fear of the unknown outweighs that. Nobody wants to be the one to take the risk. That leaves the question open. The potential savings are obvious, but the downside of a yield collapse is larger for an incumbent than the upside of a cheaper building. ## Why is the semiconductor industry so risk-averse? The executive called the caution well founded. When you commit tens of billions of dollars, you want to keep doing things the way they have been done for decades. He said this is true of many industries, not just semiconductors. The cost is a kind of indoctrination. New engineers arrive, are taught the process flow, and treat it as gospel. The flow works, so nobody has a strong reason to challenge it. His point was that a process that worked for decades is not automatically the best way to build a chip today. He also contrasted chip design with fabrication. Design, he suggested, has maybe more capacity to take risk, because experiments are cheaper. Fabrication has less. ## Is the bottleneck tools, or something else? The conversation started with a partnership between Intel and Elon Musk on a proposed fab, which Musk has called Terafab. The executive said Musk sees enormous demand for silicon, compute, and memory, and concluded his businesses will need a lot of it. Intel's view was that it could help him bring up a fab faster, given how intricate the process is. The interviewer suggested the [real limit is tool supply](https://goremy.ai/blog/articles/intel-terafab-musk-partnership-chip-tool-bottleneck), so a new fab would not add net silicon to the world but might secure guaranteed supply for its owner. The executive agreed in part, then widened the picture. A fab needs a lot of power, water, and consumables, plus raw fab space and clean room capacity. The interviewer noted these can scale in ways tools cannot. The executive said some scale more than others, but yes. Near the end, the interviewer suggested Intel should lock in tool commitments, much as Nvidia has reportedly done with memory and other components. The executive said that with hindsight Intel would have invested more a year ago, and that knowing what it knows now, it will invest more. ## What does this mean for people building with AI? Compute demand is pushing on a supply chain that is slow and expensive to expand. If fab costs keep doubling, the price and availability of advanced silicon stay tied to a handful of players who can afford the equipment. Any credible change in process flow, lithography use, or facility design would matter to anyone planning around future chip supply. Nothing in this discussion announces such a change. It is an executive saying the question deserves serious attention. ## Frequently Asked Questions ### How fast are fab costs rising? According to the Intel executive, the cost to build a fab has roughly doubled every four to five years over the last 20 to 40 years. Lithography costs have grown even faster than that overall rate. ### How much does an EUV scanner cost? A high-end EUV scanner and its associated equipment cost about $400 million today, per the executive. That is the figure he used to illustrate why patterning is the most expensive module in the fab. ### Is Intel planning to build fabs without clean rooms? No such plan was stated. The executive raised clean rooms as an example of an assumption worth questioning, and said no incumbent would willingly test it because of the risk to yield and productivity. ### Does more tool supply solve the capacity problem? Only partly. Tools are a major bottleneck, but the executive also named power, water, consumables, and raw clean room space as inputs a fab needs in large amounts.